1999 imp, inc. 408-432-9100/www.impweb.com 1 key features applications u pagers u cellular/gsm/phs phones u instrumentation u wireless terminals u battery powered systems u medical instruments u linear post-regulators u pin compatible with telcom t c1054/1055/1186 u lower dropout voltage for long battery life ?imp2054: 70mv vs. telcom tc1054 120mv ?imp2055: 160mv vs. telcom tc1055 250mv ?IMP2186: 250mv vs. telcom tc1186 400mv u power saving shutdown mode ?0.2? shutdown current u error output ?low battery detection ?processor reset u superior load regulation ?0.32% u long battery life ?33? no load ground current u accurate output voltage ? 2.5% over temperature u low drift output: 40ppm/ c u guaranteed minimum output current ?imp2054: 60ma ?imp2055: 110ma ?IMP2186: 160ma u over-current and over-temperature protection u compact sot-23a-5 package imp205 imp205 4/55, imp2 4/55, imp2 1 1 86 86 p ower m anagement 60ma/1 60ma/1 1 1 0ma/1 0ma/1 60ma 60ma super lo super lo w dr w dr opout cmos opout cmos r r egulat egulat or or s wit s wit h batt h batt er er y lif y lif e e ext ext ending shutdo ending shutdo wn mode and wn mode and err err or output or output the imp2054, imp2055 and IMP2186 high performance cmos low dropout voltage regulators offer superior dropout voltage performance and load regulation characteristics as compared to the pin compatible tc1054/1055/1186 devices offered by telcom semiconductor. dropout voltage performance has been improved by up to 40%. load regulation and power supply psrr have been optimized. load regulation is typically 0.32% and psrr is 53db at 1khz. a logic input controlled shutdown mode extends system battery life by reducing quiescent current to 0.2 m a maximum. the shutdown mode can be initiated by a system microcontroller. the regulators were designed with ease of use and stability in mind. stability is guaranteed for 0.47 m f and greater load capacitors with an esr up to 5 w . ceramic or tantalum capacitors can be used. three devices with different guaranteed output current specifications are available: imp2054 (60ma), imp2055 (110ma) and IMP2186 (160ma). each device has output voltage options of 2.5v, 2.7v, 2.85v, 3.0v, 3.3v, 3.6v and 4.0v. typical application 1 m f 1m w 1 m f + v in v out imp2054 imp2055 IMP2186 error shutdown* control 1 3 5 4 2 shdn 2054/55_02.eps gnd v out * tie to v in if not used.
2 408-432-9100/www .impweb.com 1999 imp , inc. imp205 imp205 4/55, imp2 4/55, imp2 1 1 86 86 imp20 54 / 5 5 IMP2186 v in shdn 1 v out 5 3 error 4 gnd 2 2054/55_01.eps so t -23a * r e b m u n t r a p e g a k c a p t u p t u o e g a t l o v ) v ( t u p t u o t n e r r u c ) a m ( n w o d t u h s n i p t s u j d a n i p r o r r e g a l f t u p t u o e c n e r e f e r n i p s s a p y b g n i k r a m e g a k c a p a b c d t / k u j 5 . 2 - 4 5 0 2 p m i 5 - a 3 2 t o s 5 . 2 0 6 l l r a x x t / k u j 7 . 2 - 4 5 0 2 p m i 5 - a 3 2 t o s 7 . 2 0 6 l l r b x x t / k u j 5 8 . 2 - 4 5 0 2 p m i 5 - a 3 2 t o s 5 8 . 2 0 6 l l r c x x t / k u j 0 . 3 - 4 5 0 2 p m i 5 - a 3 2 t o s 0 . 3 0 6 l l r d x x t / k u j 3 . 3 - 4 5 0 2 p m i 5 - a 3 2 t o s 3 . 3 0 6 l l r e x x t / k u j 6 . 3 - 4 5 0 2 p m i 5 - a 3 2 t o s 6 . 3 0 6 l l r f x x t / k u j 0 . 4 - 4 5 0 2 p m i 5 - a 3 2 t o s 0 . 4 0 6 l l r g x x t / k u j 5 . 2 - 5 5 0 2 p m i 5 - a 3 2 t o s 5 . 2 0 1 1 l l t a x x t / k u j 7 . 2 - 5 5 0 2 p m i 5 - a 3 2 t o s 7 . 2 0 1 1 l l t b x x t / k u j 5 8 . 2 - 5 5 0 2 p m i 5 - a 3 2 t o s 5 8 . 2 0 1 1 l l t c x x t / k u j 0 . 3 - 5 5 0 2 p m i 5 - a 3 2 t o s 0 . 3 0 1 1 l l t d x x t / k u j 3 . 3 - 5 5 0 2 p m i 5 - a 3 2 t o s 3 . 3 0 1 1 l l t e x x t / k u j 6 . 3 - 5 5 0 2 p m i 5 - a 3 2 t o s 6 . 3 0 1 1 l l t f x x t / k u j 0 . 4 - 5 5 0 2 p m i 5 - a 3 2 t o s 0 . 4 0 1 1 l l t g x x t / k u j 5 . 2 - 6 8 1 2 p m i 5 - a 3 2 t o s 5 . 2 0 6 1 l l y a x x t / k u j 7 . 2 - 6 8 1 2 p m i 5 - a 3 2 t o s 7 . 2 0 6 1 l l y b x x t / k u j 5 8 . 2 - 6 8 1 2 p m i 5 - a 3 2 t o s 5 8 . 2 0 6 1 l l y c x x t / k u j 0 . 3 - 6 8 1 2 p m i 5 - a 3 2 t o s 0 . 3 0 6 1 l l y d x x t / k u j 3 . 3 - 6 8 1 2 p m i 5 - a 3 2 t o s 3 . 3 0 6 1 l l y e x x t / k u j 6 . 3 - 6 8 1 2 p m i 5 - a 3 2 t o s 6 . 3 0 6 1 l l y f x x t / k u j 0 . 4 - 6 8 1 2 p m i 5 - a 3 2 t o s 0 . 4 0 6 1 l l y g x x l e e r d n a e p a t s e t a c i d n i t / * e d o c e t a d = x x s p e . 3 0 t _ 5 5 / 4 5 0 2 r e b m u n n i p e m a n n o i t c n u f 1 v n i . t u p n i y l p p u s d e t a l u g e r n u 2 d n g . l a n i m r e t d n u o r g 3 n d h s g n i r u d . w o l c i g o l a s i n d h s n e h w d e r e t n e s i e d o m n w o d t u h s a . t u p n i l o r t n o c n w o d t u h s 0 . 2 o t s p o r d t n e r r u c t n e c s e i u q d n a v 0 o t s l l a f e g a t l o v t u p t u o e h t n w o d t u h s m . a 4 r o r r e s i t u p t u o e h t n e h w w o l s e o g t a h t t u p t u o n i a r d n e p o n a . t u p t u o g a l f n o i t a l u g e r - f o - t u o . % 5 y l e t a m i x o r p p a y b e c n a r e l o t - f o - t u o 5 v t u o e g a t l o v t u p t u o s p e . 1 0 t _ 5 5 / 4 5 0 2 pin configuration pin descriptions ordering infor mation
1999 imp , inc. 408-432-9100/www .impweb.com 3 imp205 imp205 4/55, imp2 4/55, imp2 1 1 86 86 input v oltage . . . . . . . . . . . . . . . . . . . . . . . . . 7v output v oltage . . . . . . . . . . . . . . . . . . . . . . . . 0.3v to v in + 0.3v maximum v oltage on any pin . . . . . . . . . . . . 0.3v to (v in + 0.3v) shutdown v oltage (shdn) . . . . . . . . . . . . . . shdn v in + 0.3v operating junction t emperatur e range . . . 40 c < t j < 125 c storage t emperatur e . . . . . . . . . . . . . . . . . . . 65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . internally limited note: t j = junction t emperatur e, t a = ambient t emperatur e these ar e str ess ratings only and functional operation is not implied. exposur e to absolute maximum ratings for pr olonged time periods may affect device r eliability . all voltages ar e with r espect to gr ound. v in = v out +1v , i l = 100 m a, c l = 1 m f , shdn > v i h , t a = 25 c, unless otherwise noted. bold/ blue specifications apply for junction temperatur e range 40 c < t j < 125 c. notes: 1. v r is the r egulated output voltage: 2.5v , 2.7v , 2.85v , 3.0v , 3.3v , 3.6v or 4.0v . 2. dr opout v oltage is defined as the differ ence between in and out when v r dr ops 2% below its nominal value. 3. specifications which would otherwise be affected by self-heating of the die ar e tested at a constant die temperatur e by using low duty cycle pulse testing. 3. psrr guaranteed by design. r e t e m a r a p l o b m y s s n o i t i d n o c n i m p y t x a m s t i n u e g n a r e g a t l o v t u p n i v n i 0 c t < j 5 2 1 < c 0 5 . 6 v 0 4 c t < j 5 2 1 < c 0 5 . 6 t n e r r u c t u p t u o m u m i x a m i x a m o 4 5 0 2 p m i 0 6 a m 5 5 0 2 p m i 0 1 1 6 8 1 2 p m i 0 6 1 e g a t l o v t u p t u o d e x i f v t u o 1 e t o n v r % 5 . 2 v r % 5 . 0 v r % 5 . 2 + v ) 2 e t o n ( e g a t l o v t u o p o r d v n i v - o i l 0 0 1 = m a 1 v m i l a m 0 2 = 7 1 3 2 i l a m 0 5 = 0 6 0 7 i l ) 6 8 1 2 p m i , 4 5 0 2 p m i ( a m 0 0 1 = 0 9 0 6 1 i l ) 6 8 1 2 p m i ( a m 0 5 1 = 3 4 1 0 5 2 t n e r r u c t n e c s e i u q ) t n e r r u c d n u o r g ( d a o l o n 3 3 0 5 m a t n e r r u c y l p p u s n w o d t u h s i d s n i v 0 = n d h s t j 5 2 c 2 . 0 2 m a t n e i c i f f e o c e r u t a r e p m e t t u p t u o 0 4 m p p / c n o i t a l u g e r l a m r e h t 4 0 . 0 w / % n o i t a l u g e r e n i l v r v 1 + v n i v 6 5 7 3 0 . 0 5 3 . 0 % s p e . a 2 0 t _ 5 5 / 4 5 0 2 absolute maximum ratings electrical characteristics
4 408-432-9100/www .impweb.com 1999 imp , inc. imp205 imp205 4/55, imp2 4/55, imp2 1 1 86 86 v in = v out +1v , i l = 100 m a, c l = 1 m f , shdn > v i h , t a = 25 c, unless otherwise noted. bold/ blue specifications apply for junction temperatur e range of 40 c < t j < 125 c. notes: 1. v r is the r egulated output voltage: 2.5v , 2.7v , 2.85v , 3.0v , 3.3v , 3.6v or 4.0v . 2. dr opout v oltage is defined as the differ ence between in and out when v r dr ops 2% below its nominal value. 3. specifications which would otherwise be affected by self-heating of the die ar e tested at a constant die temperatur e by using low duty cycle pulse testing. 4. psrr guaranteed by design. r e t e m a r a p l o b m y s s n o i t i d n o c n i m p y t x a m s t i n u : n o i t a l u g e r d a o l 4 5 0 2 p m i i l 0 0 1 = m a m 0 5 o t a 2 3 . 0 0 . 2 % 5 5 0 2 p m i i l 0 0 1 = m a m 0 0 1 o t a 2 3 . 0 0 . 2 6 8 1 2 p m i i l 0 0 1 = m a m 0 5 1 o t a 2 3 . 0 0 . 3 e i d n w o d t u h s l a m r e h t e r u t a r e p m e t 0 5 1 c s i s e r e t s y h n w o d t u h s l a m r e h t 2 1 c n o i t c e j e r e l p p i r r r s p v n i 3 v ( o ) v 1 + v 5 2 . 0 c o 3 . 3 = m c i m a r e c f = . q e r f z h k 1 8 5 b d = . q e r f z h k 0 1 5 4 = . q e r f z h m 1 4 3 e s i o n t u p t u o z h k 0 5 o t z h 0 0 3 i l ) 4 5 0 2 p m i ( a m 0 5 = i l a m 0 0 1 = 0 8 2 m v s m r d l o h s e r h t h g i h t u p n i n d h s v 5 . 2 v n i v 5 . 6 5 4 v f o % n i d l o h s e r h t w o l t u p n i n d h s v 5 . 2 v n i v 5 . 6 5 1 v f o % n i m u m i n i m g a l f r o r r e e g a t l o v y l p p u s 5 . 1 v d l o h s e r h t g a l f r o r r e e g a t l o v v h t v 5 9 . 0 r v s i s e r e t s y h g a l f r o r r e v s y h 0 5 v m w o l t u p t u o g a l f r o r r e e g a t l o v i r o r r e a m 1 = 5 7 0 0 4 v m v o t n i t n e r r u c e s r e v e r t u o v ) n i ( v < ) t u o ( v = h g i h = n d h s n i 0 . 2 a m v ) n i ( v < ) t u o ( w o l = n d h s 7 . 2 m a t i m i l t n e r r u c t u p t u o 0 5 3 0 0 6 a m s p e . b 2 0 t _ 5 5 / 4 5 0 2 electrical characteristics
imp205 imp205 4/55, imp2 4/55, imp2 1 1 86 86 t ypical characteristics 1999 imp , inc. 408-432-9100/www .impweb.com 5 figur e 1. imp2055 psrr at i load = 100ma figur e 2. imp2055 psrr at i load = 1ma psrr (db) frequency (hz) 2054/55_04.eps 1 10 100 1k 10k 100k 10 20 30 40 60 80 50 70 90 psrr (db) frequency (hz) 2054/55_05.eps 1 10 100 1k 10k 100k 10 20 30 40 60 80 50 70 100 90 figur e 3. line t ransient response figur e 4. enable input response v o u t 2 0 5 4 / 5 5 _ 1 2 . e p s 5 0 m v / d i v 2 0 m s / d i v d v i n = 1 v 0 v o u t p u t 2 0 5 4 / 5 5 _ 1 3 . e p s 1 v / d i v 5 v / d i v 1 0 0 m s / d i v 0 v e n a b l e figur e 5. load t ransient response (50ma step) figur e 6. load t ransient response (100ma step) v o u t 2 0 5 4 / 5 5 _ 0 9 . e p s 2 5 m v / d i v 2 0 m a / d i v 5 0 m s / d i v l o a d p u l s e v o u t 2 0 5 4 / 5 5 _ 1 0 . e p s 2 5 m v / d i v 5 0 m a / d i v 5 0 m s / d i v l o a d p u l s e
imp205 imp205 4/55, imp2 4/55, imp2 1 1 86 86 t ypical characteristics application infor mation 6 408-432-9100/www .impweb.com 1999 imp , inc. 2 0 5 4 / 5 5 _ 1 1 . e p s 1 0 0 m a / d i v 1 0 0 m s / d i v figur e 7. output short cir cuit response the imp2054, imp2055 and IMP2186 have been designed to of fer exceptionally low dr opout voltage, superior load r egulation and minimum quiescent power . shutdown mode a battery-life-extending mode is available. thr ough the active low shutdown pin, shdn, the r egulator can be enabled or turned of f. the r egulator is shutdown (turned of f) when shdn is low and enabled (turned on) when shdn is high. the shutdown signal can be supplied fr om a cmos gate or fr om an i/o port of a micr ocontr oller . during shutdown, the output voltage falls to 0v and the supply curr ent is typically only 200na. if the shutdown mode is not needed, shdn should be connected dir ectly to the r egulator input voltage pin. error open drain output error is driven low whenever v out falls out of r egulation by mor e than 5 per cent typically . this condition may be caused by low input voltage, output curr ent limiting, or thermal limiting. the error thr eshold is 5% below rated v out r egar dless of the pr ogrammed output voltage value (e.g. error = v ol at 4.7v (typical) for a 5.0v r egulator and 2.85v (typical) for a 3.0v r egula - tor). error output operation is shown in figur e 8 . note that error is active when v out falls to v th , and inactive when v out rises above v th by v hys . as shown in figur e 9 , error can be used as a battery low flag, or as a micr ocontr oller reset signal (with the addition of timing capacitor c 2). r1 x c 2 should be chosen to maintain error below v ih of the pr ocessor reset input for at least 200ms to allow time for the system to stabilize. output capacitor the imp2054, imp2055 and IMP2186 wer e designed for stable operation with a wide range of capacitor values and type. the output capacitor should be above 0.47 m f . a 1 m f value is r ecom - mended. ceramic or tantalum capacitors ar e suitable with an esr up to 5 w . ther mal shutdown an on-chip thermal pr otection cir cuit shuts the ldo r egulator of f when the die temperatur e exceeds 150 c. ther e is a built in 12 c hyster esis. the r egulator will r emain of f until the die temperatur e dr ops to appr oximately to 138 c.
imp205 imp205 4/55, imp2 4/55, imp2 1 1 86 86 application infor mation 1999 imp , inc. 408-432-9100/www .impweb.com 7 figur e 8. error output operation figur e 9. t ypical application cir cuit 1 m f r1 1m w c1 1 m f c2 0.2 m f + + + + v in v out imp2054 imp2055 IMP2186 error shutdown* control 1 3 5 4 2 shdn 2054/55_15.eps gnd v out ba ttlow or reset v + * t ie to v in if unused. c2 required only if error is used as a processor reset signal (see text). v out v th v ih v ol err or hysteresis (v hys ) 2054/55_14.eps
imp205 imp205 4/55, imp2 4/55, imp2 1 1 86 86 8 408-432-9100/www .impweb.com 1999 imp , inc. notes pr oject
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